1. Field of the Invention
The present invention relates to a pulse generating circuit and, more particularly, to an improvement of a circuit that generates a pulse signal in response to a change in level of an input signal.
2. Description of the Prior art
Such a circuit is widely employed in, for example, a semiconductor memory circuit as an address transition detecting circuit. The circuit generates a pulse by detecting the switching of an address signal or an input signal. The pulse is used to reset an internal memory circuit by discharging a word line, precharging and equalize bit line pairs, and so on. Such a circuit is disclosed in, e.g., Japanese Patent Laid-Open Publication No. 5-54660.
Referring now to FIG. 1, the circuit cited delay circuits D51 and D52, normal inverter gates G55, G56, G57 and G511, NOR gates G58 and G59, and an active-low AND gate G510.
The delay circuit 51 is made up of two inverter gates G51 and G52 and capacitors C51 and C52. The inverter gate G51 has a P-channel transistor P51 having a narrow gate channel width, and an N-channel transistor N51 having a broad gate channel width. The inverter gate G52 has a P-channel transistor P52 having a broad gate channel width, and an N-channel transistor N52 having a narrow gate channel width. The other delay circuit D52 is identical in configuration with the delay circuit D51 and will not be described specifically in order to avoid redundancy. The circuit receives an input signal 501 and produces an output signal 502.
The input signal 502 is fed to the input of the inverter gate G51 whose output is connected to the input of the inverter gate G52. The output of the inverter gate G52 is connected to the input of the inverter gate G56 whose output is connected to one input of the NOR gate G58. The input signal 501 is connected to the other input of the NOR gate G58 also. The capacitor C51 is connected at one end to a power source potential and at the other end to a node 503, i.e., the junction between the inverter gates G51 and G52. The capacitor C52 is connected at one end to ground potential and at the other end to a node 504, i.e., the junction between the inverter gates G52 and G56.
Further, the input signal 501 is applied to the input of the normal inverter gate G55 whose output is connected to the input of the delay circuit D52. The output of the delay circuit D52 is connected to the input of the normal inverter gate G57 whose output is connected to one input of the NOR gate G59. The input of the delay circuit D52 is connected to the other input of the NOR gate 59. The output of the NOR gate G58 and that of the NOR gate G59 are respectively connected to the two inputs of the active-low AND gate G510. The output of the AND gate G510 is connected to the normal inverter gate G511.
Referring now to FIG. 2, there is shown the waveforms of signals to appear at the various nodes of the circuit shown in FIG. 1. There are shown in FIG. 6, the input signal 501, the output signal 502, a signal 503 output from the inverter gate G51, a signal 504 output from the inverter gate G52, a signal 505 output from the normal inverter gate G55, a signal 506 output from the inverter gate G53, a signal 507 output from the inverter gate G54, a signal 508 output from the normal inverter gate G57, a signal 509 output from the NOR gate G59, a signal 510 output from the normal inverter gate G56, a signal 511 output from the NOR gate G58, and a signal 512 output from the AND gate 510.
A specific operation of the above circuit will be described with reference to FIGS. 1 and 2. Assume that the input signal 501 changes from its low level to its high level. Then, the node 503 of the delay circuit D51 goes low immediately due to the inverter gate G51 whose N-channel transistor N51 has a high ability (current drive ability). The node 504 goes high immediately due to the inverter G52 whose P-channel transistor P52 has a high ability. The node 510 connected to the inverter G52 via the normal inverter gate G56 goes low while the node 511, i.e., the output of the NOR gate G58 remains in its low level.
On the other hand, the node 505, i.e., the output of the normal inverter G55 goes low at the rising edge of the input signal 501. The node 506 of the delay circuit D52 goes high slowly due to the inverter gate G53 whose P-channel transistor P53 has a low ability, and a load ascribable to the capacitor C53. The node 507 goes low slowly due to the inverter gate G54 whose N-channel transistor N54 has a low ability, and a load ascribable to the capacitor C54. The node 508, i.e., the output of the normal inverter gate G57 goes high. The node 509, i.e., the output of the NOR gate G59 goes high at the rising edge of the input signal 501, and then goes low with a delay of D provided by the delay circuit D52.
The active-low AND gate G510 ANDs the waveforms appearing on the nodes 509 and 511, and then the inverter G511 inverts the output of the AND gate 510. As a result, the inverter G511 produces the output signal 502 in the form of a pulse having a width D at the rising edge of the input signal 501.
When the input signal 501 goes low, the delay circuits D51 and D52 performs a procedure opposite to the above procedure. Consequently the circuit outputs a pulse having the width D as the output signal 502 at the falling edge of the input signal 501.
As stated above, the conventional circuit of FIG. 1 is capable of outputting a pulse of desired width D at each of the rising and falling edges of the input signal 501. However, assume that two or more short pulses are consecutively applied to the circuit as the input signal 501 by accident, as shown in FIG. 3 specifically. Then, the circuit produces a wrong pulse different from the expected pulse (,or the pulse having a width D) for the following reasons.
As shown in FIG. 3, the node 503 of the delay circuit D51 goes high at the falling edge of the first pulse of the input signal 501. Subsequently, the node 503 goes low at the rising of the second pulse of the input signal 501. At this instant, the level of the node 504 is lowered by the inverter G52. If the lowered level of the node 504 is lower than the threshold voltage of the P-channel transistor of the normal inverter gate G56, then a notch appears, as represented by the waveform of the node 510. As a result, the output of the NOR gate G58 has its width reduced by the notch. This is also true with the other delay circuit D52.
In short, the conventional circuit relies on the inverter in charging and discharging the node of the individual delay circuit. Therefore, if the pulse width of the input signal is smaller than the delay completing time of the delay circuit, and if the reset start signal (the falling edge of the input signal 501) is later in timing than the charging and discharging operation of the inverter, then the above notch appears and prevents the expected waveform from being output. An increase in the number of stages of the delay circuits D51 and D52 would aggravate this problem because it would delay the reset start signal more.
It is a common practice with a semiconductor memory device to match the promotion of the discharge of a word line, short-circuiting of a bit line pair, charge up, activation of data sense amplifier and so forth to the pulse width D of the output signal 502. Therefore, the pulse smaller in width than the expected pulse makes it impossible to keep a period of time necessary for the above operation of the memory device. Consequently, erroneous information is transferred to the memory device and prevents it from operating correctly.